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VHDL (VHSIC Hardware Description Language)
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FIPS 172-1 - (VHDL), VHSIC Hardware Description Language
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VHDL: VHSIC Hardware Description Language
VHSIC Hardware Description Language (VHDL) is commonly used as a design-entry language for FPGAs and ASICs in electronic design automation of digital circuits.
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VHDL (VHSIC hardware description language) is commonly used as a design-entry language for field-programmable gate arrays and application-specific integrated circuits in electronic design automation of digital circuits.

History VHDL was originally developed at the behest of the United States United States Department of Defense in order to document the behavior of the Application-specific integrated circuit that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details.

The idea of being able to simulate this documentation was so obviously attractive that Logic simulation were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract Random Access Memory, counter, and arithmetic blocks out of the code, and implement them according to what the user specifies. Thus, the same VHDL code could be synthesized differently for lowest cost, highest power (computing) efficiency, highest speed, or other requirements.

VHDL borrows heavily from the Ada (programming language) in both concepts (for example, the slice notation for indexing part of a one-dimensional array) and syntax. VHDL has constructs to handle the parallelism inherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL is strongly-typed and Case sensitivity. There are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including nand and nor, in order to represent directly operations which are common in hardware. VHDL also allowsarrays to be indexed in either direction (ascending or descending) because both conventions are used in hardware, whereas Ada (like most programming languages) provides ascending indexing only. The reason for the similarity between the two languages is that the United States Department of Defense required as much as possible of the syntax to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada.

The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical (integer and real data type), logical (bit and Boolean datatype), character (computing) and time, plus arrays of bit called bit_vector and of character called string (computer science).

A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE 1164, which defined the 9-value logic types: scalar std_ulogic and its vector version std_ulogic_vector.

The second issue of IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc.

Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules.

In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design extensions.

Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and microwave circuit design extensions.

In June 2006, VHDL Technical Committee of Accellera (delegated by IEEE to work on next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of 'case' and 'generate' statements, incorporation of VHPI (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions.

Discussion VHDL is a fairly general-purpose language, although it requires a simulator on which to run the code. It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a testbench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. This is similar to the capabilities of the Verilog. VHDL is a Strong typing language, and as a result is considered by some to be superior to Verilog. In fact there has always been quite an intense debate which amounts to a Flaming (Internet)#Holy Wars amongst developers over which is the superior language. However, both languages make it easy for the unwary and inexperienced to produce code that simulates successfully, but that cannot be synthesized into a real device, or else is too large to be practicable. A particular pitfall in both languages is the accidental production of transparent latches rather than Flip-flop (electronics) as storage elements.

The key advantage of VHDL when used for systems design is that it allows the behaviour of the required system to be described (modelled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behaviour, working together at the same time). This is unlike many of the other computing languages such as BASIC, Pascal, C, or lower-level assembly language which runs at machine code level, which all run sequentially, one instruction at a time on von Neumann architectures.

A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.

Getting started As with any hardware or software language, becoming proficient in VHDL requires a commitment to study and practice. Although background in a computer programming language (such as C) is helpful, it is not essential. Today, free VHDL simulators are readily available, and although these are limited in functionality compared to commercial VHDL simulators, they are more than sufficient for independent study. If the user's goal is to learn Register transfer level coding, i.e. design hardware circuits in VHDL (as opposed to simply document or simulate circuit behavior), then a synthesis/design package is also essential to the learning process.

As with VHDL simulators, free FPGA synthesis tools are readily available, and are more than adequate for independent study. Feedback from the synthesis tool gives the user a feel for the relative efficiencies of different coding styles. A schematic/gate viewer shows the user the synthesized design as a navigable netlist diagram. Many FPGA design packages offer alternative design input methods, such as block-diagram (schematic) and state-diagram capture. These provide a useful starting template for coding certain types of repetitive structures, or complex state-transition diagrams. Finally, the included tutorials and examples are valuable aids.

Nearly all FPGA design and simulation flows support both Verilog and VHDL, allowing the user to learn either or both languages. Here is a list of free design & simulation packages for VHDL/Verilog:

{| class="wikitable"|-!Vendor!Trial Software!License!Simulator!Synthesizer!RTL view!Gate view|-|Actel|Libero gold|one year free license|ModelSim Actel Edition|Synplify Actel Edition|No|*yes|-|Aldec|Active-HDL (Student Edition)|one year free license|Aldec (mixed language) Student|All Synthesis (interfaces)|yes|yes|-|Altera|Quartus II web edition|6 months renewable free license|ModelSim Altera Edition|Altera Quartus II|yes|*yes|-|Lattice|ispLever starter|6 months renewable free license|Precision/Synplify Lattice Edition||No|yes|-|Mentor|none|free license|ModelSim PE Student Edition|no|yes|no|-|Xilinx|ISE webpack|free license|+ISE Simulator|Xilinx XST|yes|*yes|-|Blue Pacific|BlueHDL|free license|BlueSim|?|?|?|}

* Limited to vendor's device-database
+ If Modelsim is installed on the computer, the ISE software can call ModelSim's features if desired.

Code examples In VHDL, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures and configurations.

A simple Logic gate in VHDL would look something like this:

-- (this is a VHDL comment)

-- import std_logic from the IEEE librarylibrary IEEE;use IEEE.std_logic_1164.all;

-- this is the entityentity ANDGATE is port ( IN1 : in std_logic; IN2 : in std_logic; OUT1: out std_logic); end ANDGATE;architecture RTL of ANDGATE is

begin

OUT1